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TRF7970A
SLOS743K – AUGUST 2011 – REVISED APRIL 2014
www.ti.com
Table 6-44. IRQ Status Register (0x0C) for NFC and Card Emulation Operation
Function: Information available about TRF7970A IRQ and TX/RX status
Default: 0x00 at POR = H or EN = L, and at each write to the ISO Control Register 0x01. It is also automatically reset at the end of a read
phase. The reset also removes the IRQ flag.
Bit
B7
B6
B5
B4
B3
B2
B1
B0
Name
Irq_tx
Irg_srx
Irq_fifo
Irq_err1
Irq_sdd
Irq_rf
Irq_col
Irq_col_err
Function
IRQ set due to end of TX
IRQ set due to RX start
Signals the FIFO level
Protocol error
SDD completed
RF field change
RF collision avoidance
finished
RF collision avoidance not
finished successfully
Description
Signals that TX is in progress. The flag is set at the start of TX but the interrupt
request (IRQ = 1) is sent when TX is finished.
Signals that RX SOF was received and RX is in progress. The flag is set at the
start of RX but the interrupt request (IRQ = 1) is sent when RX is finished.
Signals FIFO high or low as set in the Adjustable FIFO IRQ Levels (0x14)
register
Any protocol error
SDD (passive target at 106 kbps) successfully finished
Sufficient RF signal level for operation was reached or lost
The system has finished collision avoidance and the minimum wait time is
elapsed.
The external RF field was present so the collision avoidance could not be
carried out.
6.14.3.3.2 Interrupt Mask Register (0x0D) and Collision Position Register (0x0E)
Table 6-45. Interrupt Mask Register (0x0D)
Default: 0x3E at POR = H and EN = L. Collision bits reset automatically after read operation.
Bit
B7
B6
Name
Col9
Col8
Function
Bit position of collision MSB Supports ISO14443A
Bit position of collision
Description
B5
B4
B3
B2
B1
B0
En_irq_fifo
En_irq_err1
En_irq_err2
En_irq_err3
En_irq_col
En_irq_noresp
Interrupt enable for FIFO
Interrupt enable for CRC
Interrupt enable for Parity
Interrupt enable for Framing
error or EOF
Interrupt enable for collision
error
Enables no-response
interrupt
Default = 1
Default = 1
Default = 1
Default = 1
Default = 1
Default = 0
Table 6-46. Collision Position Register (0x0E)
Function: Displays the bit position of collision or error
Default: 0x00 at POR = H and EN = L. Automatically reset after read operation.
Bit
B7
B6
B5
B4
B3
B2
B1
Name
Col7
Col6
Col5
Col4
Col3
Col2
Col1
Function
Bit position of collision MSB
Description
ISO14443A mainly supported, in the other protocols this register shows the bit
position of error. Either frame, SOF/EOF, parity or CRC error.
66
B0
Col0
Detailed Description
Bit position of collision LSB
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